`timescale 1ns/100ps
module shifter(clk,nrst,din,dout);
input clk,nrst;
input din;
output reg dout;
always@(posedge clk or negedge nrst) begin:shifter_with_nreset
if(~nrst) dout<=1'b0;
else dout<=din;
end
endmodule